> Your question would require a very long answer to be somewhat exhaustive, > so here the express version. Start by reading Documentation/cachetlb.txt > from the kernel sources. You can find plenty of discussions related to > this code in the linux-mips and linux-kernel archives - especially the > subtle points aren't exactly documented ;-) Thanks, I'll check that out. However a new complexity has arisen. It turns out that in addition to not having access to the MMU, we do not have access to cp0. I'm afraid that this would require even more rewriting of the kernel. Although I started this to learn something, there might be more involved in this than I am prepared for. Cameron
