On Mon, Feb 07, 2005 at 09:10:12AM +0100, Rojhalat Ibrahim wrote:
> With a slightly extended patch it actually works. But afterwards
> I get a lot of Illegal instructions and Segmentation faults, where
> there shouldn't be any. Below is the patch I used.
> --- linux/arch/mips/mm/c-r4k.c 2005-01-03 10:23:27.000000000 +0100
> +++ linux-2.6.10/arch/mips/mm/c-r4k.c 2005-02-07 09:04:27.000000000 +0100
> @@ -566,9 +566,17 @@
>
> if (!cpu_has_ic_fills_f_dc) {
> unsigned long addr = (unsigned long) page_address(page);
> - r4k_blast_dcache_page(addr);
> + if (addr)
> + r4k_blast_dcache_page(addr);
> + else
> + r4k_blast_dcache();
> if (!cpu_icache_snoops_remote_store)
> - r4k_blast_scache_page(addr);
> + {
> + if (addr)
> + r4k_blast_scache_page(addr);
> + else
> + r4k_blast_scache();
> + }
> ClearPageDcacheDirty(page);
> }
Blowing away the entire S-cache is extreme overkill. We really want to
avoid this if possible as it'll have serious performance impact. As for
the RM9000 that means we have a struct page pointer, therefore we know
the physical address of the page and can perform a selective flush on the
second level cache. See below for a patch which tries that.
Obviously this one only tries to optimize performance a bit further but
doesn't really solve the remaining problem.
Ralf
Index: arch/mips/mm/c-r4k.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/mm/c-r4k.c,v
retrieving revision 1.101
diff -u -r1.101 c-r4k.c
--- arch/mips/mm/c-r4k.c 7 Feb 2005 21:53:39 -0000 1.101
+++ arch/mips/mm/c-r4k.c 8 Feb 2005 00:18:17 -0000
@@ -566,9 +566,21 @@
if (!cpu_has_ic_fills_f_dc) {
unsigned long addr = (unsigned long) page_address(page);
- r4k_blast_dcache_page(addr);
- if (!cpu_icache_snoops_remote_store)
- r4k_blast_scache_page(addr);
+
+ if (addr)
+ r4k_blast_dcache_page(addr);
+ else
+ r4k_blast_dcache();
+
+ if (!cpu_icache_snoops_remote_store) {
+ if (addr)
+ r4k_blast_scache_page(addr);
+ else {
+ addr = page_to_pfn(page) << PAGE_SHIFT;
+ addr = CKSEG + (addr & ~((1UL << 24) - 1));
+ r4k_blast_scache_page_indexed(addr);
+ }
+ }
ClearPageDcacheDirty(page);
}
