Hello,
Manish Lachwani a écrit :
For chip revisions 1.0 and 1.1, there are some changes to the memory management subsystem for the kernel to work on the board (dual core). As already known, these versions dont support Shared state.
I had made those changes to the 2.4.21 kernel. Maybe you can take a look at those changes and port them to 2.6 appropriately. However, there is more sanity in 1.2 version
Actually, my question was not really Linux-specific. On the second core, I will not use the MMU, because this core will not run Linux, but a custom code. Both cores will share informations through KSEG0, so I need to maintain coherency between caches. What should I do in order to do that ? Is it enough to set cache mode for KSEG0 to 4 (in the CONFIG register) ?
I have only 1.0 and 1.1 cores, on home-made boards, so there's no way to switch to 1.2.
BTW, do you have pointers, papers, information about a system running Linux on a core, and some custom code on a second core, in order to have real-time on the second core with very low latency ?
Thanks,
Thomas -- PETAZZONI Thomas - thomas.petazzoni@xxxxxxxx http://thomas.enix.org - Jabber: thomas.petazzoni@xxxxxxxxx http://kos.enix.org, http://sos.enix.org Fingerprint : 0BE1 4CF3 CEA4 AC9D CC6E 1624 F653 CB30 98D3 F7A7
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