In file include/asm-mips/pci.h
there are some functions for dma if the I/O model is non-coherent.
for example:
pci_map_sg
pci_unmap_sg
These two functions exist for ide dma.
Before the dma transfer, pci_map_sg will map the memory space covered by sg_table,
and it will flush and invalidate cache indexed by that memory space.
After the dma transfer, pci_unmap_sg also needs to be called to flush and invalidate
the same cache. But I do not know why the second flush will be demanded.
I think that in the interval between the two flush, there would be nothing to access
the memory covered by the dma. But it is not the case.
I want to know what can access that memory and I need some help.
