> It's not. The 4kc processor when running with the
> BEV bit in the status
> register cleared will try to find it's exception
> vectors at address
> KSEG0, so there would have to be *some* code mapped
> there. With BEV=1
> exception vectors would be located in the firmware
> as pointed out by
> Steve in his answer. Firmware means something like
> flashmemory and running
> uncached, so will be prohibitivly slow. I just
> can't believe a system to
> be that missdesigned!
Well actually I have memories that can be accessed by
KSEG0, but they are very limited:
start size type
----------------------------
0x00000000 - 128Ko - RAM
0x01000000 - 128Ko - FLASH
0x1fc00000 - 128Ko - ROM
Therefore I could use this internal RAM to store
exception vectors.
My fears are on running kernel in KSEG2.
I'm thinking of trying this configuration:
I'm going to use 2 TLB entries to map definetively
kernel in KSEG1:
* 1 entry to map kernel code in FLASH (16Mo),
* 1 entry to map kernel data in SDRAM (8Mo).
space virtual-add physical-add size
----------------------------------------------
Code 0xC0000000 0x30000000 16Mo
Data 0xC1000000 0x20000000 8Mo
I will set PAGE_OFFSET to 0xA1000000, therefore all
physicall address convertion will result in SDRAM.
Hopefully, this macro is only used to make translation
between physical and virtual spaces. I grep it and it
seems to be the case.
Do you think that I can dig at this way ?
Thanks,
Francis
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