On Mon, 22 Nov 2004, Manish Lachwani wrote: > However, the crash still occurs. I dont think your patch was intended to > fix the problem that I see below (resulting in crash). Certainly, it wasn't, but it couldn't have hurt, either. > Data bus error, epc == 801f83b8, ra == 80323f04 The reason are cp0 hazards, likely leading to an incorrect mapping. Try the following patch; already applied to the mainline as obviously correct. Maciej patch-mips-2.6.10-rc1-20041112-mips-tlb-ehb-0 diff -up --recursive --new-file linux-mips-2.6.10-rc1-20041112.macro/arch/mips/mm/tlbex.c linux-mips-2.6.10-rc1-20041112/arch/mips/mm/tlbex.c --- linux-mips-2.6.10-rc1-20041112.macro/arch/mips/mm/tlbex.c 2004-11-23 19:52:53.000000000 +0000 +++ linux-mips-2.6.10-rc1-20041112/arch/mips/mm/tlbex.c 2004-11-23 19:58:31.000000000 +0000 @@ -448,7 +448,8 @@ L_LA(_split) #define i_bnez(buf, rs, off) i_bne(buf, rs, 0, off) #define i_move(buf, a, b) i_ADDU(buf, a, 0, b) #define i_nop(buf) i_sll(buf, 0, 0, 0) -#define i_ssnop(buf) i_sll(buf, 0, 2, 1) +#define i_ssnop(buf) i_sll(buf, 0, 0, 1) +#define i_ehb(buf) i_sll(buf, 0, 0, 3) #if CONFIG_MIPS64 static __init int in_compat_space_p(long addr) @@ -799,12 +800,12 @@ static __init void build_tlb_write_rando default: /* * Others are assumed to have one cycle mtc0 hazard, - * and one cycle tlbwr hazard. + * and one cycle tlbwr hazard or to understand ehb. * XXX: This might be overly general. */ - i_nop(p); + i_ehb(p); i_tlbwr(p); - i_nop(p); + i_ehb(p); break; } }
