Hi Manish & Ralf, the code below is from tian_ge.c: /* * This is the 1.2 revision of the chip. It has fix for the * IP header alignment. Now, the IP header begins at an * aligned address and this wont need an extra copy in the * driver. This performance drawback existed in the previous * versions of the silicon */ reg_data_1 = TITAN_GE_READ(0x103c + (port_num << 12)); reg_data_1 |= 0x40000000; TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1); reg_data_1 |= 0x04000000; TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1); mdelay(5); reg_data_1 &= ~(0x04000000); TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1); mdelay(5); According to the RM9000 user manual, register 0x103c (and 0x203c and 0x303c), named TTPRI0, contains eight four-bit fields, each of which is a packet priority value. This would be used to find the priority for incoming packets. Given the register description in the cpu manual, I cannot make any sense of the code above. Whoever did that, would you care to explain? thanks, Thomas -- -------------------------------------------------- Thomas Koeller, Software Development Basler Vision Technologies thomas dot koeller at baslerweb dot com http://www.baslerweb.com ==============================
