In arch/mips/kerenl/smp.c, there are two tables defined, __cpu_number_map[]
and __cpu_logical_map[], which would appear to provide forward and backward
mapping between a set of unique but arbitrary CPU numbers and a monotonically
increasing number 0..n of indices into per-CPU data. As near as I can tell, the
only use of this is in the sb1250 code for setting up interrupt hardware. Is there
a reason why it's defined at the mips/kernel level, and not down in the SiByte
platform subtree? Is there a generic, architectural definition of how these mappings
should and should not be set up and used?
Regards,
Kevin K.
