Hi, I'm still in the process of choosing the best configurable parameters of a hardware design based on 4KEc As far as I understand, excepted alpha platforms, 4KByte pages are the de facto standard [I assume linux developers are reasonable so changing the page size to 8KB is not going to be a nightmare...] Since the mips cache is virtually indexed but physically tagged, I see two problems when the size of a cache way exceeds the size of a page: - virtual aliasing. Can only happen on R/W pages (data cache) and only when two different virtual addresses map the same physical page. An example of this is: two processes sharing a memory area; should I consider this is taken into account by linux already? - I was told the software exception handlers for tlb are much less efficient when cacheway > pagesize, forcing to flush too often. Is this true? What is, in practice, the ratio of instruction pages and data pages in a tlb? If I consider a platform like Toshiba TX39 which has d-cache four ways with total 32KBytes, it must already have the problems above. I'd like to get some more clues though... Thanks a lot, Sincerely yours, E.M.
