On Sun, May 09, 2004 at 11:09:29AM +0200, Geert Uytterhoeven wrote: > > Kernel is yesterday's CVS. gcc is 3.3.1. config is ddb5477. No > > additional patch. See below. > > > > In any case if you look at the uart code you should see there > > is a problem already. 'state' is allocated through kmalloc() which only > > gives 4-byte alignement. The only puzzling thing is that why this > > did not show up before. Maybe kmalloc() was giving 8-byte aligned block? > > AFAIK, kmaloc() always[*] returns 8-byte (or higher, for archs that need it) > aligned blocks. We got tripped by a change in 2.6.6-rc2. Before that change the kmalloc slab caches were being created with SLAB_HWCACHE_ALIGN which results in L1_CACHE_SHIFT alignment for allocations of L1_CACHE_SHIFT for slab caches that are at least that size. For the sake of S390 this behaviour was changed; new it defaults to BYTES_PER_WORD alignment which is four bytes. Fixed by defining ARCH_KMALLOC_MINALIGN as 8. Ralf Index: include/asm-mips/cache.h =================================================================== RCS file: /home/cvs/linux/include/asm-mips/cache.h,v retrieving revision 1.16 diff -u -r1.16 cache.h --- include/asm-mips/cache.h 10 Oct 2003 20:37:35 -0000 1.16 +++ include/asm-mips/cache.h 9 May 2004 12:57:38 -0000 @@ -18,4 +18,6 @@ #define SMP_CACHE_SHIFT L1_CACHE_SHIFT #define SMP_CACHE_BYTES L1_CACHE_BYTES +#define ARCH_KMALLOC_MINALIGN 8 + #endif /* _ASM_CACHE_H */
