Okay. I will have a look at tomorrow morning.
The change goes beyond just cache managment; the API also abstracts away I/O MMUs which so far are quite rare on MIPS systems - but I really hope they're going to establish themselves asap.
The Documentation/DMA-API.txt also documents how properly deal with cache alignment when using this API.
Steven, maybe that we should add another assertion to make sure we don't run into trouble with missaligned cachelines?
-Steve
