> > Basically, the PC points to the next instruction > > to > > be executed. But, in R4k, there are 8 instructions > > getting executed in parallel. Where does the PC point > > to? My understanding is that PC points to the next > > instruction that will be entered into the pipeline. > > Please correct me if i am wrong.. Ralf Baechle (ralf@linux-mips.org) writes: > The fact that instructions are issued in a pipeline is not visible in > the EPC value. Which is true, but perhaps a bit cryptic given the question. A MIPS CPU does not have a register called "PC". In the MIPS architecture, "PC" is just slang meaning "the address of this instruction" - and only makes any sense if you're prepared to say WHICH instruction you mean. There IS a register called "EPC" (for "exception PC"). When you take any kind of exception, it's the address of the first instruction which didn't get run because the CPU took the exception instead. So EPC tells you where to jump back to after the exception handler runs. Did any of that make any sense? -- Dominic Sweetman MIPS Technologies.
