The MIPS architecture specifies a single delay slot after a branch or jump. The fact that the R4000 implementation (and pretty much any of the ones following) had a pipeline in which more instructions had already entered the pipe before the branch is resolved is not relevant to the architecture specification. In the case you mention, a single instruction is executed after the branch, as architecturally required, and any subsequent instructions in the pipe are killed. /gmu On Thu, 2003-12-18 at 22:01, karthikeyan natarajan wrote: > Hi All, > > If this is not a right forum to ask this Question, > > please redirect me to the appropriate one... > Since R4000 is using the 8 stage pipeline, three > instructions are already entered into the pipeline > when the branch instruction is executed. Out of these > three instructions, the first instruction will be > executed for sure. > > My question is: > What happens to the other two instruction that are > in the delay slots? are they nullified? > Could anyone please shed some light on this. > > Thanks much, > -karthi > > ===== > The expert at anything was once a beginner > > ________________________________________________________________________ > Yahoo! Messenger - Communicate instantly..."Ping" > your friends today! Download Messenger Now > http://uk.messenger.yahoo.com/download/index.html > -- Michael Uhler, Chief Technology Officer MIPS Technologies, Inc. Email: uhler@mips.com Pager: uhler_p@mips.com 1225 Charleston Road Voice: (650)567-5025 FAX: (650)567-5225 Mountain View, CA 94043 Mobile: (650)868-6870 Admin: (650)567-5085
