>>>>> On Tue, 12 Aug 2003 08:51:18 +0200, Thiemo Seufer <ica2_ts@csv.ica.uni-stuttgart.de> said: >> The option -march=r4600 seems to make gcc 3.3.x choose >> MIPS_ISA_MIPS3. Thiemo> Which is ok, because the available ISA has little to do with Thiemo> the actually used register width. Thiemo> If the intention is to use mfc0 for 32bit kernels and dmfc0 Thiemo> for 64bit, the check should probably be Thiemo> #ifdef __mips64 Thiemo> # define MFC0 dmfc0 Thiemo> # define MTC0 dmtc0 Thiemo> #else Thiemo> # define MFC0 mfc0 Thiemo> # define MTC0 mtc0 Thiemo> #endif Thanks for your explanations. Perhaps the code should be fixed is __BUILD_clear_ade in entry.S, but I'm not sure. Does anybody know why __BUILD_clear_ade uses MFC0 and REG_S though other parts using mfc0 and sw ?
