For MIPS32 and MIPS64 processors (the 5K is MIPS64), it is architecturally defined and required, and the compatibility verification testing verifies it (and, yes, we do run compatibility verification testing on our own cores). /gmu On Mon, 2003-08-11 at 12:57, David Kesselring wrote: > Is this reg, supposed to be the same among all processor or does it > differ? > > On 11 Aug 2003, Mike Uhler wrote: > > > Bit 0 of Config1 is FPU-present. Bit 4 is "Performance counters > > present". I guarantee you that the 5K family implements this > > pattern. > > > > /gmu > > > > > > On Mon, 2003-08-11 at 11:28, David Kesselring wrote: > > > Has anyone else built linux 2.4 for a 5k or 5kf core? When comparing cpu.h > > > and the MIPS64 5K Processor Core Family Software Users Manual it doesn't > > > look to me that the c0-config1 reg is defined the same way. Am I reading > > > something wrong? For example in the spec FPU flag is bit0 while in cpu.h > > > it is bit4. Seems pretty basic. > > > > > > David Kesselring > > > Atmel MMC > > > dkesselr@mmc.atmel.com > > > 919-462-6587 > > -- > > > > Michael Uhler, Chief Technology Officer > > MIPS Technologies, Inc. Email: uhler@mips.com Pager:uhler_p@mips.com > > 1225 Charleston Road Voice: (650)567-5025 FAX: (650)567-5225 > > Mountain View, CA 94043 Mobile: (650)868-6870 Admin: (650)567-5085 > > > > > > > > > > David Kesselring > Atmel MMC > dkesselr@mmc.atmel.com > 919-462-6587 -- Michael Uhler, Chief Technology Officer MIPS Technologies, Inc. Email: uhler@mips.com Pager:uhler_p@mips.com 1225 Charleston Road Voice: (650)567-5025 FAX: (650)567-5225 Mountain View, CA 94043 Mobile: (650)868-6870 Admin: (650)567-5085
