hi, r4k_cache_flush_sigtrap seems not enough for RM7000 cpus because there is a writebuffer between L1 dcache & L2 cache,so the written back block may not be seen by icache. This small patch fixes crashes of my Xserver on ev64240. --- r4kcache.h.ori 2003-07-31 09:51:01.000000000 +0800 +++ r4kcache.h 2003-07-31 09:51:57.000000000 +0800 @@ -94,6 +94,9 @@ ".set noreorder\n\t" ".set mips3\n" "1:\tcache %0,(%1)\n" +#ifdef CONFIG_CPU_RM7000 + "sync\n\t" +#endif "2:\t.set mips0\n\t" ".set reorder\n\t" ".section\t__ex_table,\"a\"\n\t"
