On Thu, 5 Jun 2003, Kevin D. Kissell wrote: > > > > 1) clocks on different CPUs don't have the same frequency > > > > 2) clocks on different CPUs drift to each other > > > > 2) some fancy power saving feature such as frequency scaling > > > > > > > > But I think for a foreseeable future most MIPS SMP machines > > > > don't have the above issues (true?). And it is probably worthwile > > > > to synchronize count registers for them. > > > > > > 1) and 2) affect most SGI systems. > > > > > > > Assuming SGI systems represent the past of MIPS, we are still ok > > future-wise. :) > > I personally think it would be foolish to assume that future MIPS > MP systems will not be subject to one or more such constraint. Depending on the system in use it may be easier to get a suitable external clock reference, e.g. a chipset timer. If an access to it would be slow, it could be cached on timer interrupts and extended with processors' timers. -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available +
