There are many benefits of having perfectly synchronized CPU count registers on SMP machines. I wonder if this is something which have been done before, and if this is feasible. Apparently, this scheme won't work if any of the following conditions are true: 1) clocks on different CPUs don't have the same frequency 2) clocks on different CPUs drift to each other 2) some fancy power saving feature such as frequency scaling But I think for a foreseeable future most MIPS SMP machines don't have the above issues (true?). And it is probably worthwile to synchronize count registers for them. I think some pseudo code like the below could get the job done: CPU 0: send interrupt to all other CPUs and ask them to sync count wait for all other CPUs to gather at rendevous point flip a flag set count to 0 other CPUs: trapped by IPI reach the rendevous point (busy spin locking) wait for the flip of the flag set count to 0 I wonder after the above code how synchronized are the count regsiters. Are they perfectly synchronized or still differ by a few counts? Any comments? Jun
