>>>>> On Wed, 16 Apr 2003 15:46:54 +0200 (MET DST), "Maciej W. Rozycki" <macro@ds2.pg.gda.pl> said: >> AFAIK TX49's SYNC instruction correctly flushes the write buffer. macro> That would be an overkill; we only need to enforce strong macro> ordering here. Hmm... But SYNC is a only TX49 instruction that enforce completions of preceding read operations. (TX49 have "non-blocking load" feature which allows non-cached read/write to overtake preceding cached read) I can imagine three configurations: 1. Enable CONFIG_CPU_HAS_SYNC and disable CONFIG_CPU_HAS_WB. In this case, wmb/rmb/mb/iob/wbflush macro all issues a SYNC instruction. 2. Disable CONFIG_CPU_HAS_SYNC and enable CONFIG_CPU_HAS_WB, In this case, wmb/rmb macro does nothing and mb/iob/wbflush macro calls __wbflush(). 3. Enable both CONFIG_CPU_HAS_SYNC and CONFIG_CPU_HAS_WB, In this case, wmb/rmb macro issues a SYNC instruction, mb/iob macro calls __wbflush() and wbflush macro do both. In the case 2 and 3, __wbflush() must be implemented with SYNC instruction and/or bc0f loop. I think the case 1 is good and enough for TX49. >> No bc0f loop is required. macro> But an external buffer may be attached to a TX49 core, IIRC, macro> so if it is the case for TOSHIBA_RBTX4927, it's obviously macro> needed. Although I'm not sure whether TX49 core can be integrated with such an external write buffer, all TX49XX (not TX39) I have ever seen does not have it. --- Atsushi Nemoto
