On Thu, 3 Apr 2003, Ralf Baechle wrote: > I know of one machine where changing the size of the cacheline is supposed > not to work, that's the MIPS Magnum 4000 and it's close relatives. Hmm, why -- is such a change observable externally in any way? Of course you can't switch the other way if the s-cache uses a line width of 16 bytes. Maybe that's the case with the Magnum? > Anyway, I put the check there for the unlikely case there are broken > systems out there. In practice I assume vendors were aware of this > problem and the check is purely theoretical and for paranoid correctness's > sake. Still V3.0 should be taken into account. > It seems like changing the configuration to larger cache lines where > possible should improve performance somewhat. If all the cache code is Why? It isn't that obvious especially as a p-cache miss costs a single cycle only. > working truly correct we also should no longer see VCE exceptions on > R4000SC processors - the reason why Indys are still a valuable test tool. As are DECstations which use the opposite endianness -- so you can test code both ways. -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available +
