>From the gcc sources, the compiler generates the lwl,lwr etc. in the block move code in gcc/config/mips/mips.c ( output_block_move ). There is an option -mmemcpy which tells gcc to use a memcpy compiled in with the sources for this block move instead of gcc genetrating code. The problem however with this is that arch/mips/lib/memcpy.S is optimized using lwl,lwr,swl,swr. If this can be modified so that lwl,lwr,swl,swr is used if enabled as a kernel option, it might work very well. Any ideas / suggestions? Thanks Ranjan -----Original Message----- From: Ralf Baechle [mailto:ralf@linux-mips.org] Sent: Wednesday, March 12, 2003 5:34 PM To: Richard Hodges Cc: Ranjan Parthasarathy; 'linux-mips@linux-mips.org' Subject: Re: Disabling lwl and lwr instruction generation On Wed, Mar 12, 2003 at 04:50:53PM -0800, Richard Hodges wrote: > I got lwl and lwr from a memcpy() with two void pointers... > > I quickly changed those to the (aligned) structure pointers instead, and > then memcpy() changed to ordinary word loads and stores. > > So, is somebody starting a toolchain for that new Chinese CPU? :-) Wouldn't be the first processor without lwl/lwr instructions. There have been a few that didn't implement it for silly bean^Wgate counting issues others have done it for patent and licensing reasons. (Afair MIPS's patent is about to expire and IBM's prior art patent in the same area is even way older but that legalese ...) Ralf
