Hi all,
This patch sets up irq's properly. The author of this code
apparently didn't understand the ugly hacks that are going on
in bridge_irq_type.* (startup_bridge_irq() and friends).
So, they were:
(a) allocating a stupid IRQ number (that collided with
something else in my case). This doesn't matter at all,
since the timer interrupt comes through different channels
to PCI device interrupts.
(b) not calling setup_irq(), which meant, among other things,
it wasn't appearing in /proc/interrupts. setup_irq()
was crashing on them on startup, because startup_bridge_irq()
was trying to do all kinds of PCI initialization on it (IIRC).
Basically, if you pick an IRQ number less than BASE_PCI,
startup_bridge_irq() will ignore it, and all works dandy :)
The Right Solution TM would probably involve some other
hw_interrupt_type like cpu_irq_type, or something.
Cheers,
Andrew
Index: arch/mips/sgi-ip27/ip27-timer.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/sgi-ip27/ip27-timer.c,v
retrieving revision 1.1.2.4
diff -u -r1.1.2.4 ip27-timer.c
--- arch/mips/sgi-ip27/ip27-timer.c 2 Dec 2002 00:24:51 -0000 1.1.2.4
+++ arch/mips/sgi-ip27/ip27-timer.c 30 Jan 2003 22:38:48 -0000
@@ -90,13 +90,11 @@
return retval;
}
-#define IP27_TIMER_IRQ 9 /* XXX Assign number */
-
void rt_timer_interrupt(struct pt_regs *regs)
{
int cpu = smp_processor_id();
int cpuA = ((cputoslice(cpu)) == 0);
- int irq = IP27_TIMER_IRQ;
+ int irq = CPU_TIMER_IRQ;
irq_enter(cpu, irq);
write_lock(&xtime_lock);
@@ -198,7 +196,7 @@
irq->handler = no_action;
/* setup irqaction */
-// setup_irq(IP27_TIMER_IRQ, irq); /* XXX Can't do this yet. */
+ setup_irq(CPU_TIMER_IRQ, irq);
}
void __init ip27_time_init(void)
Index: include/asm-mips64/sn/sn0/ip27.h
===================================================================
RCS file: /home/cvs/linux/include/asm-mips64/sn/sn0/ip27.h,v
retrieving revision 1.9.2.1
diff -u -r1.9.2.1 ip27.h
--- include/asm-mips64/sn/sn0/ip27.h 27 Jun 2002 14:21:24 -0000 1.9.2.1
+++ include/asm-mips64/sn/sn0/ip27.h 30 Jan 2003 22:39:00 -0000
@@ -88,7 +88,8 @@
#define CPU_RESCHED_B_IRQ 1
#define CPU_CALL_A_IRQ 2
#define CPU_CALL_B_IRQ 3
-#define BASE_PCI_IRQ 4
+#define CPU_TIMER_IRQ 4
+#define BASE_PCI_IRQ 5
#define SN00_BRIDGE 0x9200000008000000
#define SN00I_BRIDGE0 0x920000000b000000
