On Tue, Jan 28, 2003 at 01:30:03PM +0100, Maciej W. Rozycki wrote: > Actually I have a datasheet for the Vr4121 (which is a Vr4120 plus some > glue logic for specific peripherals) and it explicitly states whenever > cp0.EPC points to a preceding branch/jump of a faulting instruction, the > cp0.Cause.BD bit is set. Maybe there is an errata sheet available. Honestly I'd not expect this to be documented in a NEC manual - they basically look like the description of the processor core is the same for basically all the Vr4xxx processors and SOCs. > Additionally the processor is "nice" enough to implement the MIPS III ISA > (with the MIPS16 extension) except ll/sc, lld/scd, sigh... So the > emulation would need to be ported to the 64-bit kernel if we were to > support this processor in the 64-bit mode. Maximum agreement on the "sigh" part ... Ralf
