Jun Sun wrote:
> A couple of nit-picking points ...
>
> On Wed, Dec 11, 2002 at 09:20:28AM +0100, Carsten Langgaard wrote:
> > Index: arch/mips/mips-boards/generic/pci.c
> > ===================================================================
> > RCS file: /home/cvs/linux/arch/mips/mips-boards/generic/pci.c,v
> > retrieving revision 1.5.2.4
> > diff -u -r1.5.2.4 pci.c
> > --- arch/mips/mips-boards/generic/pci.c 28 Sep 2002 18:28:44 -0000 1.5.2.4
> > +++ arch/mips/mips-boards/generic/pci.c 11 Dec 2002 08:11:56 -0000
> > @@ -405,6 +405,12 @@
> > ".set\treorder");
> >
> > irq = *(volatile u32 *)(KSEG1ADDR(BONITO_PCICFG_BASE));
> > + __asm__ __volatile__(
> > + ".set\tnoreorder\n\t"
> > + ".set\tnoat\n\t"
> > + "sync\n\t"
> > + ".set\tat\n\t"
> > + ".set\treorder");
> > irq &= 0xff;
> > BONITO_PCIMAP_CFG = 0;
> > break;
>
> Would a higher level macro such as __sync or fast_mb be better here?
I have already send a new patch to Ralf, because he argued for the same thing.
These macros was just not around, when I made this fix.
>
> > Index: arch/mips/mips-boards/malta/malta_int.c
> > ===================================================================
> > RCS file: /home/cvs/linux/arch/mips/mips-boards/malta/malta_int.c,v
> > retrieving revision 1.8.2.6
> > diff -u -r1.8.2.6 malta_int.c
> > --- arch/mips/mips-boards/malta/malta_int.c 5 Aug 2002 23:53:34 -0000 1.8.2.6
> > +++ arch/mips/mips-boards/malta/malta_int.c 11 Dec 2002 08:11:57 -0000
> > @@ -91,6 +91,9 @@
> > {
> > unsigned int data,datahi;
> >
> > + /* Mask out corehi interrupt. */
> > + clear_c0_status(IE_IRQ3);
> > +
> > printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
> > printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n"
> > , regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr);
> > @@ -125,7 +128,6 @@
> >
> > /* We die here*/
> > die("CoreHi interrupt", regs);
> > - while (1) ;
> > }
> >
> > void __init init_IRQ(void)
>
> I think corehi interrupt should be blocked from the beginning. I seem to
> remember a board errata itme that recommands not using it.
>
I have found quite a lot of bugs, with the corehi interrupt enabled. It should never
happen, so it indicates a fatal error, if it does.
It's true that on an early revision of some PLD code, there was a bug around the corehi
interrupt. If you got such a board, I suggest you update your PLD code.
>
> Jun
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