Ralf Baechle wrote:
> On Wed, Dec 04, 2002 at 10:09:54AM +0100, Kevin D. Kissell wrote:
>
> > For those on the list who don't understand Carsten's sense
> > of humour, I think that was missing a smiley! ;-)
> > I mean, sure, we'd like to move more people toward SDE,
> > but "force" is putting it a bit strongly! And if those directives
> > are really being used unconditionally, I worry that the code
> > being generated is likewise emitting MIPS32 instructions
> > that won't work on the "ghost fleet" of abandoned workstations
> > now running Linux on R4K/R5K CPUs.
>
> A fix is now in CVS. With this fix only compiling a kernel for MIPS32
> and MIPS64 CPUs will require a the new tools.
>
> Everybody satisfied?
Not quite, I afraid.
I would like to be able to compile a 64-bit kernel, using the
MIPS32/MIPS64 config1 register, but I don't have a MIPS64 compliant n64
compiler (assembler). So I need the hardcoded ".word" opcode version, we
previously had.
Something like this:
/*
* This should be changed when we get a compiler that support the MIPS32
ISA.
*/
#define read_mips32_cp0_config1() \
({ int __res; \
__asm__ __volatile__( \
".set\tnoreorder\n\t" \
".set\tnoat\n\t" \
"#.set\tmips64\n\t" \
"#mfc0\t$1, $16, 1\n\t" \
"#.set\tmips0\n\t" \
".word\t0x40018001\n\t" \
"move\t%0,$1\n\t" \
".set\tat\n\t" \
".set\treorder" \
:"=r" (__res)); \
__res;})
>
> I was quite amazed how much email in just like 2 days this change was
> producing, even people binutils 2.8 started yelling ...
>
> Ralf
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