On Mon, Nov 25, 2002 at 04:47:33PM +0100, Maciej W. Rozycki wrote: > > MIPS64 extends that to also support instruction address matches; the > > granularity can be set anywhere from 8 bytes to 4kB; in addition ASID > > matching and a global bit can be used for matching. A MIPS64 CPU can > > support anywhere from 0 to 4 such watch registers. > > Actually up to eight -- for all dmfc0/dmtc0 3-bit "sel" values, if I read > it correctly. Correct but I don't know of any CPU that actually uses more than 4 of the possible 8 sets atm. So we're both right :) > > The global bit stuff would only be useful for in-kernel use, I think. The > > ASID thing could be used to implement watchpoints for an entire process, not > > just per thread though I doubt there is much use for something like that. > > Well, there are two options only -- either use global matching or ASID > matching. What else would you expect? Do you mean lazy vs immediate > switching? Basically there would be two possibilities, associate the debugging state of a process with it's thread_struct or with it's mm_struct. The latter would have a little less impact on the context switching performance, the first be a bit more flexible. Ralf
