On Tue, Oct 15, 2002 at 05:36:29PM +0200, Maciej W. Rozycki wrote: > Well, the kernel changes should be trivial, with no performance impact if > written carefully, so they might get included even if only a few people > are interested. Send a proposal. Here's patch for the kernel. Tested on a VR41XX, but my glibc patch needs some cleanup and so will be posted seperately. I thought "explicit is better than implicit" and thus added many small changes depending on CONFIG_CPU_USERSPACE_LLSC_EMUL before every eret. The changes in tlbex-r4k.S are not stricly necessary, since in current code k1 always ends up with a CP0_ENTRYLO value with has bit31 == 0, which is sufficient for the glibc-patch. Also, the 'move k1,zero' does not add any overhead and thus could be done unconditionally. But i thought that adding the #ifdef CONFIG_CPU_USERSPACE_LLSC_EMUL prevents possible future changes from accidentally breaking this. The patch is only for the VR41XX. I'm not shure what other CPUs fall into the same category. If I read binutils/opcodes/mips-opc.c correctly, then the TX39XX, while not being ISA2, has beql. Please tell me if the patch is acceptable. Possible options: - don't mess with tlbex-r4k.S - or unconditonally replace the 'nop's before 'eret's in tlbex-r4k.S with 'move k1,zero' plus a comment - drop the CONFIG_CPU_USERSPACE_LLSC_EMUL configuration option and always clear k1 in RESTORE_SP_AND_RET for the VR41XX Regards, Johannes
