Dominic Sweetman wrote: > Carsten Langgaard (carstenl@mips.com) writes: > > > I think we have a problem with the PREF instructions spread out in the > > memcpy function. > > Not really. The MIPS32 manual (for example): > > "PREF does not cause addressing-related exceptions. If it does happen > to raise an exception condition, the exception condition is > ignored. If an addressing-related exception condition is raised and > ignored, no data movement occurs." Is a bus error exception an address related exception ? I'm afraid some implementation think it's not. > > PREF never generates a memory operation for a location with an > uncached memory access type." > > For a Linux user program, at least, memory pages are "memory-like": > reads are guaranteed to be side-effect free, so any outlying > prefetches are harmless. It's hard to see any circumstance where an > accessible cacheable location would lead to bad side-effects on read. What about an UART RX register, we might loose a character ? You can also configure you system, so you get a external interrupt from you system controller in case of a bus error, there is no way the CPU can relate this interrupt to the prefetching. > > > -- > Dominic Sweetman, > MIPS Technologies (UK) - formerly Algorithmics > The Fruit Farm, Ely Road, Chittering, CAMBS CB5 9PH, ENGLAND > phone: +44 1223 706200 / fax: +44 1223 706250 / direct: +44 1223 706205 > http://www.algor.co.uk -- _ _ ____ ___ Carsten Langgaard Mailto:carstenl@mips.com |\ /|||___)(___ MIPS Denmark Direct: +45 4486 5527 | \/ ||| ____) Lautrupvang 4B Switch: +45 4486 5555 TECHNOLOGIES 2750 Ballerup Fax...: +45 4486 5556 Denmark http://www.mips.com
