On Thu, 5 Sep 2002, Kevin D. Kissell wrote: > of some algorithms. MIPS was rather unique in having made > a "binary compatible" transition from 32 to 64-bits. Does anyone > know what's being done with C integer binding on the AMD > "Hammer" architecture? They're looking at the same problem, > 10 years further on. Well, SPARC is another mature example that works this way. And the PA-RISC, PPC, and S390 ports may have similar experiences, but I don't know the details. MIPS is quite unique with the n32 ABI as the ABI is 64-bit but with 32-bit addressing. I'll see if and how they handle such a case, but it's likely they have plain 32-bit and plain 64-bit ABIs only. BTW, I've found an interesting type size analyzis in the SUSv2 at: 'http://www.usenix.org/publications/login/standards/10.data.html' and they simply opt for LP64 for 64-bit systems. -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available +
