I've taken it upon myself to re-write some interrupt handling code. It's a mess, and it needs cleaning. So, I need to understand a few things about how interrupts are handled. I'd appreciate it if someone could tell me if I'm on the right track here... As far as I can see, the default for the mips arch is to support up to 128 interrupts, tho that can be changed with a #define NR_IRQS at compile time. The mapping of an interrupt source to a particular number is pretty much up to the board-specific code, it looks like. An interrupt handler must be registered with set_except_vector(0, ...) which must return a numeric code in the range of 0..NR_IRQS -- it can do this in any way it wants, including limited function calls (ie there is a stack in place). The irq_desc array of irq_desc_t structures is where the magic happens. The value returned by the interrupt handler is used as an index into this array to do the dispatch a specific handler. The 'status' and 'action' fields are pretty much self-explanatory. The 'handler' field seems to point to a set of function pointers used for enabling/disabling the IRQ. But what is 'depth' for? Boards seem to set it to either 0 or 1 commonly, but I don't see why. I also don't see how IRQ sharing is accomplished... Is this pretty much how it all works? Matt -- Matthew D. Dharm Senior Software Designer Momentum Computer Inc. 1815 Aston Ave. Suite 107 (760) 431-8663 X-115 Carlsbad, CA 92008-7310 Momentum Works For You www.momenco.com
