The kernel code to support /dev/random on Mips on currently uses 'jiffies' as an
input to random number process. The code has a special case to use the high
precision TSC on x86 when it is availble. (see linux/drivers/char/random.c :
add_timer_randomness() ) It looks like it would only take a few lines of code to
use the CP0_COUNT register on Mips to perform a similar function.
We have a headless embedded system which has none of tradional sources of
random entropy such as keyboard, mouse or disk activity. Currently our only
option is to use the network interrupt, but I know this is considered a poor
source since an attacker could generating a known sequence of packets. If we
could increase the resolution of the timing then it would make it harder to
exploit.
Has anyone tried this?
Jon Burgess
