Ralf Baechle wrote: > On Wed, Jul 10, 2002 at 04:49:00PM -0700, H. J. Lu wrote: > > > > See the crash scene. Anybody knows the cause? It is strange to see the > > > reserved exception. > > > > > > > The 2.4 kernel checked out around Jul 4 09:28 PDT works fine on Malta. > > Jun's patch certainly is correct for some MIPS32 CPUs; others may get > away without this one. Previous experience with pipeline hazards on MIPS > processors has shown that at times hazards may change even between minor > revisions of a CPU; documentation isn't always trustworthy about such > minor details of the pipeline. I actually discovered the hazard problem on a 4Kc, based on some older RTL, but the hazard some how disappear on a newer revision. So you are absolutely right. > > Ralf -- _ _ ____ ___ Carsten Langgaard Mailto:carstenl@mips.com |\ /|||___)(___ MIPS Denmark Direct: +45 4486 5527 | \/ ||| ____) Lautrupvang 4B Switch: +45 4486 5555 TECHNOLOGIES 2750 Ballerup Fax...: +45 4486 5556 Denmark http://www.mips.com
