I can see the 'dma_cache_inv_pc' routines (in the arch/mips/mm cache files), in almost every incarnation, is actually doing a write-back invalidation, why ? My first thought was, that this will never work for the PCI devices doing DMA, so I was wondering why it actually does work. And the answer is, that this routine isn't used by the PCI DMA functions, no matter what the DIRECTION of the DMA transfer is. Has anyone got an idea why the while PCI DMA stuff is implemented this way (only using write-back invalidations) ? I would expect that we did a write-back invalidation of the D-cache, when the direction was PCI_DMA_TODEVICE and only did invalidation of the D-cache, when the direction was PCI_DMA_FROMDEVICE. /Carsten -- _ _ ____ ___ Carsten Langgaard Mailto:carstenl@mips.com |\ /|||___)(___ MIPS Denmark Direct: +45 4486 5527 | \/ ||| ____) Lautrupvang 4B Switch: +45 4486 5555 TECHNOLOGIES 2750 Ballerup Fax...: +45 4486 5556 Denmark http://www.mips.com
