On Thursday 28 March 2002 14:01, Maciej W. Rozycki wrote: > But the I/O ASIC chip is smart enough to merge data from the 8-bit ROM > device without problems and present four consecutive bytes as 32-bit > quantities to the host CPU. A simple 4 to 1 mapping is easy, even for the average hardware developer :-) > Why couldn't it do the same for the LANCE? > Host memory addresses are generated on behalf of the LANCE by the I/O ASIC > anyway. Probably because this would have made the IOASIC 0.0034 cents more expensive? > Of course not all designers have a clue, sigh... A brief study of > available documentation suggests no merging mode was implemented for the > LANCE and bit 0 of addresses generated is simply hardwired to 0. :-( That's my interpretation as well. Greetings, Harald
