On Wed, Feb 20, 2002 at 03:46:32PM +0100, Maciej W. Rozycki wrote: > > The context register is actually intended to be used for indexing a flat > > 4mb array of pagetables on a 32-bit processor. It's a bit ill-defined > > on R4000-class processors as it assumes a size of 8 bytes per pte, so > > cannot be used in the Linux/MIPS kernel without shifting bits around. > > Ill??? I think someone was just longsighted enough not to limit PTEs to > 38-bit physical addresses. A shift costs a single cycle if we want to > save memory. The idea of the register was to directly generate the address of a PTE. An extra instruction in TLB exception handlers isn't only visible in performance, it also means introducing constraints on the address itself - an arithmetic shift by one bit for 4 byte PTEs will result in the two high bits of the address being identical, an arithmetic shift will make the high bit a null etc. Just on 32-bit kernels on 64-bit hw you're lucky, you have a bit 32 in c0_context which will be shifted into bit 31. Messy? Ralf
