On Fri, 15 Feb 2002, Ralf Baechle wrote: > In practice sync just isn't good enough. Most systems these days use > an I/O bus like PCI which uses posted writes or have some other > non-strongly ordered memory model. Which is why something wmb() or > mb() aren't good enough in driver. I'm just having a nice discussion It depends on what a driver needs. They are perfectly sufficient and actually needed for host bus devices if you need to be sure writes and/or reads happen in order. It's only when a side-effect of a write needs to happen immediately a write-back flush is needed. It doesn't happen that often. AFAIK, PCI only allows posted writes -- it doesn't allow write or read reordering, so mb() and friends are sufficient. Are there any busses we support or are going to in foreseeable future that have a weak ordering model? > about this topic with SGI's IA64 people; we have to come up with a > portable and efficient ABI. ABI? API, I suppose. I can't see anything special here -- drivers already know the bus they are on and they know if it needs any specific handling. I don't think it's possibly to define general functions for I/O buses as actions depend on the device that's being addressed. E.g. for a PCI device a driver needs to perform a read from one of the device's assigned regions and which location exactly, depends on what memory or registers the device implements (surely it can't read one that implies side effects). It can't just do an arbitrary read from a location decoded to the bus. Anyway, will my patch get applied or do we have to wait until the discussion concludes? The patch doesn't affect any I/O bus-specific operations, so it's orthogonal. Also a new API is surely a 2.5 item. -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available +
