On Thu, Jan 31, 2002 at 01:17:39PM +0100, Maciej W. Rozycki wrote: > Certain DECstation models have a write-back buffer that needs to be > handled explicitly. For example rmb() is "1: bc0f 1b" for the R3220 WB > chip. Wmb() is null, certainly, as the buffer is strongly-ordered. See > arch/mips/dec/wbflush.c for details. Just as an aside that isn't directly relevant to DECstations. To date all MIPS _processors_ are strongly ordered. I now know of at least one processor that implements a weakly ordered memory model, so the assumption of a strongly ordered memory model has become void for large parts of the kernel. Even before that some systems had strongly ordered processors in system environments that may reorder requests. Bugs due to surprise memory reordering are entirely unfun to debug, so be paranoid. They're out there to get you ... Ralf
