Are there any plans to provide full MIPS irq support in the general mips irq code? The only machine that appears to attempt to fully support the MIPS interrupt set currently is the gt64120/momenco_ocelot machine. It uses the define CP0_S1_INTCONTROL ($20) to get at the upper interrupt lines ( > 8 ). Anyone else find that support for this MIPS hardware would be best placed in the standard irq code rather than each machine variant having to re-implement it itself (as the irq code was in the past). Thanks, Roger Twede
