On Sat, Jan 19, 2002 at 12:27:52PM +0000, Dominic Sweetman wrote: > > H . J . Lu (hjl@lucon.org) writes: > > > > It would, in principle, be possible to save/restore k0 > > > or k1 (but not both) if no other clever solution can be found. > > > There are other VM OSes that manage to do so for MIPS, > > > for other outside-the-old-ABI reasons. It does, of course, > > > add some instructions and some memory traffic to the > > > low-level exception handling , and we would have to look > > > at whether we would want to make such a feature standard > > > or specific to a "thread-ready" kernel build. > > > > I like the read-only k0 idea. We just need to make a system call to > > tell kernel what value to put in k0 before returning to the user space. > > It shouldn't be too hard to implement. I will try it next week. > > You could, I guess, wire a TLB entry to map the thread register into > the highest virtual memory region of the machine (the top of 'kseg2'), > which is accessible in a single instruction as a negative offset from > $0. The kernel can write it through kseg0 or 64-bit equivalent, if > you're a bit careful about cache aliases. But it has to be a per thread value. > > Reading something out of the cache is pretty cheap: would that be > close enough to a 'register' to do the job? There's no change to > critical routines, that way. > This is a patch against 2.4.16. Will this restore k1 to a known per thread value? H.J. --- include/asm-mips/stackframe.h.thread Wed Dec 12 12:34:53 2001 +++ include/asm-mips/stackframe.h Sat Jan 19 11:36:38 2002 @@ -191,6 +191,7 @@ __asm__ ( lw $2, PT_R2(sp) #define RESTORE_SP_AND_RET \ + lw $27, PT_R27(sp); \ .set push; \ .set noreorder; \ lw k0, PT_EPC(sp); \ @@ -229,6 +230,7 @@ __asm__ ( lw $2, PT_R2(sp) #define RESTORE_SP_AND_RET \ + lw $27, PT_R27(sp); \ lw sp, PT_R29(sp); \ .set mips3; \ eret; \ @@ -237,6 +239,7 @@ __asm__ ( #endif #define RESTORE_SP \ + lw $27, PT_R27(sp); \ lw sp, PT_R29(sp); \ #define RESTORE_ALL \
