Well, just about k0/k1: So far as the hardware and instruction set is concerned, k0/k1 are just two of the 32 general purpose registers. There's nothing special about them and a program in user mode can read/write them. By a mere software convention, they're reserved. But this is an important software convention, because MIPS hardware does so little to help out on an exception or interrupt. Couple that to the lack of any absolute addressing mode, and any exception handler pretty much has to have a GP register it can write without saving, in order to be able to point to the register-save area. [You could, maybe, do something tricky with a negative offset from the (constant zero) $0 register and special mapping] OK, so that's one of them. The second is used to reduce the length and run-time of the tiny exception handler which is used to refill the TLB when a page translation is not loaded. The OS doesn't rely on user programs not corrupting these registers, of course: it typically uses them only in non-interruptible code sequences. But since the OS changes them under the feet of user programs, the convention that you don't use them is pretty strongly enforced. Dominic Sweetman Algorithmics Ltd
