Hi,
It seems secondary cache handling for R5000 (at least on the
O2) is quite different from the R4xxx. Unfortunately, it's detected by
this code and the cache operates in a wrong way. This patch disables
detection of a secondary cache for the R5000.
Vivien Chappelier.
diff -Naur linux/arch/mips64/mm/r4xx0.c linux.patch/arch/mips64/mm/r4xx0.c
--- linux/arch/mips64/mm/r4xx0.c Wed Jan 2 22:56:41 2002
+++ linux.patch/arch/mips64/mm/r4xx0.c Wed Jan 2 23:10:24 2002
@@ -2346,8 +2346,21 @@
int sc_present = 0;
/* Maybe the cpu knows about a l2 cache? */
- probe_scache_kseg1 = (probe_func_t) (KSEG1ADDR(&probe_scache));
- sc_present = probe_scache_kseg1(config);
+ switch(mips_cpu.cputype) {
+ case CPU_R4000SC:
+ case CPU_R4000MC:
+ case CPU_R4200:
+ case CPU_R4300:
+ case CPU_R4400SC:
+ case CPU_R4400MC:
+ case CPU_R4600:
+ case CPU_R4640:
+ case CPU_R4650:
+ case CPU_R4700:
+ probe_scache_kseg1 = (probe_func_t) (KSEG1ADDR(&probe_scache));
+ sc_present = probe_scache_kseg1(config);
+ break;
+ }
if (sc_present) {
setup_scache_funcs();
