>>>>> On Thu, 20 Sep 2001 05:16:43 +0200, Ralf Baechle <ralf@oss.sgi.com> said:
>> BTW, I can not see any point in copying FCR31 to r0. What is a
>> purpose of the cfc1 instruction?
ralf> On CPUs with imprecise exceptions a FPU exception might still be
ralf> pending and possibly be taken arbitrarily delayed. The cfc1
ralf> instruction serves as an exception barrier for such exceptions.
ralf> At this time TFP is the only CPU which features imprecise
ralf> exceptions.
I see. Thanks for your quick answer.
And I wrote wrong thing in my previous mail. What I wanted to say is:
diff -ur linux.sgi/arch/mips/kernel/process.c linux/arch/mips/kernel/process.c
--- linux.sgi/arch/mips/kernel/process.c Sun Aug 5 23:39:09 2001
+++ linux/arch/mips/kernel/process.c Thu Sep 20 12:54:52 2001
@@ -56,8 +56,10 @@
{
/* Forget lazy fpu state */
if (last_task_used_math == current) {
- set_cp0_status(ST0_CU1);
- __asm__ __volatile__("cfc1\t$0,$31");
+ if (mips_cpu.options & MIPS_CPU_FPU) {
+ set_cp0_status(ST0_CU1);
+ __asm__ __volatile__("cfc1\t$0,$31");
+ }
last_task_used_math = NULL;
}
}
@@ -66,8 +68,10 @@
{
/* Forget lazy fpu state */
if (last_task_used_math == current) {
- set_cp0_status(ST0_CU1);
- __asm__ __volatile__("cfc1\t$0,$31");
+ if (mips_cpu.options & MIPS_CPU_FPU) {
+ set_cp0_status(ST0_CU1);
+ __asm__ __volatile__("cfc1\t$0,$31");
+ }
last_task_used_math = NULL;
}
}
---
As Florian Lohoff reported, there are CPUs require this patch.
---
Atsushi Nemoto
