Barry Wu wrote:
> I meet problems about mips ide disk. I find dma mode
> is different from other platform. We have to use
> dma_cache_wback_inv and vtonocache functions to work
> under DMA mode, I read pcnet32 ethernet driver,
> it works like that. I do not know if I have to support
> ide disk dma, what I have to do?
Some MIPS'ification is needed to handle the caches.
You can try the patch below to drivers/block/ide-dma.c.
I don't know about your IDE controller (our board have
a CMD PCI-648), but it may need some special handling also.
-Tommy
--- ide-dma.c.old Tue Aug 31 09:46:14 1999
+++ ide-dma.c Mon Aug 13 20:51:57 2001
@@ -176,6 +176,13 @@
#endif
unsigned int count = 0;
+#if defined(__mips__)
+ /* MIPS: We access the dmatable through uncached addresses, so that it
+ * will be read correctly by the controller. The alternative is to flush
+ * the appropriate range at the end of this procedure.
+ */
+ table = (unsigned int *)vtonocache(table);
+#endif
do {
/*
* Determine addr and size of next buffer area. We assume that
@@ -197,6 +204,10 @@
size += bh->b_size;
}
}
+#if defined(__mips__)
+ /* MIPS: We need to flush the cache */
+ dma_cache_wback_inv(bus_to_virt(addr), size);
+#endif
/*
* Fill in the dma table, without crossing any 64kB boundaries.
* Most hardware requires 16-bit alignment of all blocks,
@@ -401,6 +412,10 @@
dmatable += (PRD_ENTRIES * PRD_BYTES);
leftover -= (PRD_ENTRIES * PRD_BYTES);
hwif->dmaproc = &ide_dmaproc;
+#if defined(__mips__)
+ /* Make sure no part of the dmatable is in the cache */
+ dma_cache_wback_inv(hwif->dmatable, PRD_ENTRIES * PRD_BYTES);
+#endif
if (hwif->chipset != ide_trm290) {
byte dma_stat = inb(dma_base+2);
@@ -430,6 +445,9 @@
}
}
if (dma_base) {
+#if defined(__mips__)
+ dma_base = KSEG1ADDR(dma_base);
+#endif
if (extra) /* PDC20246 & HPT343 */
request_region(dma_base+16, extra, name);
dma_base += hwif->channel ? 8 : 0;
