"Maciej W. Rozycki" wrote: > The MIPS architecture defines the bus error exception event for data > reads and instruction fetches only. Writes are asynchronous so errors on > them cannot be reported exactly -- some MIPS documentation recommends > using a general-purpose interrupt line for such events. > DBE is treated as ACK* on write. Some HW design manuals advise to use this fact even. Regards, Gleb.
