That bit should be the "IV" bit on the R52xx, which is actually
a control bit, not a status indication. The set value implies
that interrupt exceptions are being vectored to offet 0x200
instead of 0x180. It should not be changing on its own!
Kevin K.
----- Original Message -----
From: "Phil Thompson" <Phil.Thompson@pace.co.uk>
To: <linux-mips@oss.sgi.com>
Sent: Thursday, August 09, 2001 2:39 PM
Subject: RM5231A Cause Register Values
> In my low level assembler interrupt handler I'm detecting a Cause register
> value of 0x00800000. According to "See MIPS Run", the bit that is set
should
> be zero - but I haven't been able to find any RM5231A documentation that
> defines this bit as anything else. Any ideas?
>
> BTW, the exception is raised under fairly heavy network traffic and in
> either disable_irq_nosync() or ei_start_xmit(). The latter is in the
network
> card driver and itself contains a call to disable_irq_nosync(). I don't
> believe (although I may be wrong) that this was happening under the old
> style interrupt code.
>
> Thanks,
> Phil
