Hi, =?EUC-KR?B?sK29xbHU?= writes: > I am trying to port a linux 2.4 to R3000 based system (LSI LOGIC > SC2000). > SC2000 have caches. one is Two-way set associative or direct mapped > Instruction cache (16K) and another is Direct-mapped data cache(8K). I also spent one or two weeks with Linux on an SC2000 a while ago but had to stop due to other more important projects. I also ran into problems with the caching. Without caching I got it to boot via NFS. Anyway, at least one mistake is in this part: > ---------------lsi-cache.S-------------------------------- > > /* void flush_icache(void) */ > LEAF(flush_icache) > .set noreorder > > la a3, icache_size # 8Kbyte > lw t4, 0(a3) > > mfc0 t7, CP0_STATUS # save SR > nop > nop > > and t0, t7, ~ST0_IEC # disable interrupts > mtc0 t0, CP0_STATUS > nop > nop > > li t3, CBSYS # BBCC configuration register > lw t8, 0(t3) # save config. register > nop > > li t0, KSEG0 > or t4, t4, t0 # end of I-cache > > move t5, t0 > > 2: la t0, 3f # switch to Kseg1 > or t0, KSEG1 > jr t0 > nop > > # > # flush I-cache set 0 > # > 3: > li t0, (CFG_DCEN | CFG_ICEN) > or t0, CFG_CMODE_ITEST # I-cache set1 enable > # D-cache enable, I-cache set0 > enable > # I-cache software test > sw t0, 0(t3) > lw zero, 0(t3) > addi zero, zero, 1 > > move t0, t5 > 4: sw zero, (t0) > nop > lw zero, (t0) > addu t0, t6 > bltu t0, t4, 4b > nop Where does t6 get set? This bug already is in the LSI sample code. I think they just copied the loop code from the cache invalidation functions (where they actually do determine t6 from the cache line size) and forgot to adjust it. Best regards, Ralph -- /--------------------------------------------------------------------\ | Dr. Ralph J.K. Metzler | Convergence integrated media | |--------------------------------|-----------------------------------| | rjkm@convergence.de | http://www.convergence.de/ | \--------------------------------------------------------------------/
