Hi,
shouldnt the srl at least stall for a cycle on interlocked CPUs ?
Index: arch/mips/kernel/r4k_misc.S
===================================================================
RCS file: /cvs/linux/arch/mips/kernel/r4k_misc.S,v
retrieving revision 1.10
diff -u -r1.10 r4k_misc.S
--- arch/mips/kernel/r4k_misc.S 2000/12/14 21:39:51 1.10
+++ arch/mips/kernel/r4k_misc.S 2001/01/28 16:03:44
@@ -37,8 +37,8 @@
*/
#define LOAD_PTE(pte, ptr) \
mfc0 pte, CP0_BADVADDR; \
- srl pte, pte, 22; \
lw ptr, current_pgd; \
+ srl pte, pte, 22; \
sll pte, pte, 2; \
addu ptr, ptr, pte; \
mfc0 pte, CP0_BADVADDR; \
--
Florian Lohoff flo@rfc822.org +49-5201-669912
Why is it called "common sense" when nobody seems to have any?
