On Fri, Jan 12, 2001 at 11:48:50PM +0000, Alan Cox wrote: > > My understanding is that we don't have a standard way to probe for external > > cache (L2 or L3). So this problem is not only for MIPS32 cpus. > > Cache is very arch specific. You don't want to know how you find L2 cache > on a MacII for example 8) Actually the Indy's R4600 / R5000 second level caches also call for the use of LARTs in a while (1) loop ;-) Read the generic code had to be changed in order to support in a sane way. Ralf
