Justin Carlson wrote: > Looking at the existing clear_page implementations for r4xx0, rm7k, and mips32 > in the mips/ tree, I see everyone issuing cache op 0xd for the address range of > the page being cleared. > > I'm wondering what the purpose is of these cache flushes...given a physically > tagged dcache, my understanding of the semantics of clear_page are that it just > zeros the page, in which case the cache ops are pointless overhead. > > Especially in the mips32 case, which uses cache op 0xd, which is undefined > implementation dependent according to my mips32 spec. You are absolutely right, it is implementation dependent. I just tend to use the mips32 implementation for my R4000s as well, and here as Ralf mention it is performance improving. Actually we have included a CPU option flag (MIPS_CPU_CACHE_CDEX), what tells us if the CPU has the Create_Dirty_Exclusive CACHE operation available. So we should probably use it, now it is here :-) Thanks. > > Am I missing something here? > > Thanks, > Justin -- _ _ ____ ___ Carsten Langgaard Mailto:carstenl@mips.com |\ /|||___)(___ MIPS Denmark Direct: +45 4486 5527 | \/ ||| ____) Lautrupvang 4B Switch: +45 4486 5555 TECHNOLOGIES 2750 Ballerup Fax...: +45 4486 5556 Denmark http://www.mips.com
