On Wed, Jan 29, 2014 at 05:30:14PM -0800, Guenter Roeck wrote: > On Wed, Jan 29, 2014 at 05:12:48PM -0800, Alun Evans wrote: > > > > On 29 Jan 2014, at 11:48, Alun Evans <alun@xxxxxxxxxxxxx> wrote: > > > > > Thanks for the responses everyone, inline, > > > > > > On 29 Jan 2014, at 10:25, Guenter Roeck <linux@xxxxxxxxxxxx> wrote: > > > > > >> On Wed, Jan 29, 2014 at 05:42:24PM +0100, Jean Delvare wrote: > > >>> Hi Alun, > > >>> <snip> > > >> > > >>> Please ask Supermicro about it. > > > > > > I have put a request in… We’ll see if I get a response. > > > > > >>> If the memory slots are behind an I2C > > >>> multiplexer, ask them if the multiplexer is I2C-based or GPIO-based. If > > >>> I2C-based, ask for the multiplexer type and address. If GPIO-based, ask > > >>> for the chip name and pin numbers for the GPIOs. In both case, please > > >>> ask which GPIO combinations map to which memory slots. > > > > I inlined the above hunk with my question, and the first response was: > > > > > Received feedback; The memory address does not use mux. It is hardware defined by Intel. > > > > So I went and clarified I was not talking about the DDR physical address setup by the memory reference code, and I got: > > > > > Per our engineer; There is no hardware connecting to DIMM. > > > > I’m not sure I’ve found the right help here... > > > Actually you might have. On some HW the DIMMs are connceted to a separate > SMBus channel which is not visible to SW. > I had a quick glance into the Patsburg (c600) datasheet. The chip has up to four SMBus channels, depending on chip variant. Are you sure that you are talking to the correct one ? What do you see with lspci ? Thanks, Guenter _______________________________________________ lm-sensors mailing list lm-sensors@xxxxxxxxxxxxxx http://lists.lm-sensors.org/mailman/listinfo/lm-sensors
